NROM flash memory with a high-permittivity gate dielectric

ABSTRACT

A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate between a pair of the source/drain regions. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric can have an oxide-high-k dielectric-oxide composite structure, an oxide-nitride-high-k dielectric composite structure, or a high-k dielectric-high-k dielectric-high-k dielectric composite structure.

RELATED APPLICATION

This Application is a Divisional of U.S. application Ser. No.10/775,908, titled “NROM FLASH MEMORY WITH A HIGH-PERMITTIVITY GATEDIELECTRIC,” filed Feb. 10, 2004, (pending) which is commonly assignedand incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to nitride read only memory(NROM) flash memory device architecture.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and flash memory. One type offlash memory is a nitride read only memory (NROM). NROM has some of thecharacteristics of flash memory but does not require the specialfabrication processes of flash memory. NROM integrated circuits can beimplemented using a standard CMOS process.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

The performance of flash memory transistors needs to increase as theperformance of computer systems increases. To accomplish a performanceincrease, the transistors can be reduced in size. This has the effect ofincreased speed with decreased power requirements.

However, a problem with decreased flash memory size is that flash memorycell technologies have some scaling limitations. For example, stressinduced leakage typically requires a tunnel oxide above 60 Å. Thisthickness results in a scaling limit on the gate length. Additionally,this gate oxide thickness limits the read current and may require largegate widths.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora more scalable, higher performance flash memory transistor.

SUMMARY

The above-mentioned problems with flash memory scaling and performanceand other problems are addressed by the present invention and will beunderstood by reading and studying the following specification.

The present invention encompasses an NROM flash memory transistor with ahigh permittivity gate dielectric. The transistor is comprised of asubstrate with a plurality of source/drain regions. The source/drainregions have a different conductivity than the substrate into which theyare doped.

A high-k gate dielectric is formed on the substrate substantiallybetween the plurality of source/drain regions. The gate dielectric has ahigh dielectric constant that is greater than silicon dioxide. The gatedielectric can be an atomic layer deposited and/or evaporatednanolaminate gate dielectric. A control gate is formed on top of theoxide insulator.

Further embodiments of the invention include methods and apparatus ofvarying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of one embodiment of an NROM flashmemory cell transistor of the present invention.

FIG. 2 shows an energy-band diagram in accordance with the transistor ofFIG. 1.

FIG. 3 shows an energy-band diagram in accordance with a write operationto the transistor structure of FIG. 1.

FIG. 4 shows an energy-band diagram in accordance with an eraseoperation from the transistor structure of FIG. 1.

FIG. 5 shows a plot of tunneling current dependence on barrier heightfor various electric fields in accordance with the transistor structureof FIG. 1.

FIG. 6 shows a block diagram of an electronic system of the presentinvention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 1 illustrates a cross-sectional view of one embodiment of a nitrideread only memory (NROM) flash memory cell transistor of the presentinvention. This NROM transistor uses the high-k dielectric layer of thepresent invention as a trapping layer. In order to improve theprogramming speed and/or lower the programming voltage of an NROMdevice, it is desirable to use a trapping material with a lowerconduction band edge (i.e., a higher electron affinity) to achieve alarger offset as well as to provide for programming by direct tunnelingat low voltages.

High permittivity dielectric materials such as HfO₂ and ZrO₂ have alower conduction band edge than the prior art trapping material, siliconnitride. If HfO₂ were used as a trapping layer, the offset would be 1.7eV that is much better than the 1.2 eV associated with a nitridetrapping layer.

The transistor is comprised of two source/drain regions 101 and 102doped into the substrate 103. In one embodiment, these are n+regions andthe substrate is p-type silicon. However, the present invention is notlimited to any conductivity type.

A tunnel oxide layer 105 is formed on the substrate 103 between thesource/drain regions 101 and 102. The high dielectric constant trappinglayer 107 is formed on top of the tunnel oxide layer 105 and anotheroxide layer 109 is formed on top of the trapping layer 107. Theoxide-high-k dielectric-oxide layers 105, 107, and 109 form a compositegate insulator 100 under the polysilicon control gate 111. In oneembodiment, the nanolaminate gate insulator 100 can be fabricated by theabove-described ALD, the evaporated technique, or a combination of thetwo.

The simplest nanolaminates with high-k dielectrics are oxide-high-kdielectric-oxide composites. Since silicon dioxide has a low electronaffinity and high conduction band offset with respect to the conductionband of silicon, these nanolaminates have a high barrier, Φ, between thehigh-k dielectric and the oxide. If the trapping center energies, E_(t),in the high-k dielectrics illustrated in FIG. 2 are large then otherhigh-k dielectrics with a smaller barrier can be used.

Examples of oxide-high-k dielectric-oxide composites include: oxide-ALDHfO₂-oxide, oxide-evaporated HfO₂-oxide, oxide-ALD ZrO₂-oxide,oxide-evaporated ZrO₂-oxide, oxide-ALD ZrSnTiO-oxide, oxide-ALDZrON-oxide, oxide-ALD ZrAlO-oxide, oxide-ALD ZrTiO₄-oxide, oxide-ALDAl₂O₃-oxide, oxide-ALD La₂O₃-oxide, oxide-LaAlO₃-oxide, oxide-evaporatedLaAlO₃-oxide, oxide-ALD HfAlO₃-oxide, oxide-ALD HfSiON-oxide,oxide-evaporated Y₂O₃-oxide, oxide-evaporated Gd₂O-oxide, oxide-ALDTa₂O₅ -oxide, oxide-ALD TiO₂-oxide, oxide-evaporated TiO₂-oxide,oxide-ALD PrO₃-oxide, oxide-evaporated PrO₃-oxide, oxide-evaporatedCrTiO₃-oxide, and oxide-evaporated YSiO-oxide.

Another class of nanolaminates avoids tunneling between the trappingcenters in the nitride layer of a conventional NROM device and thecontrol gate. High-k dielectrics, in one embodiment, can be used as thetop layer in the gate insulator nanolaminate. Since they have a muchhigher dielectric constant than silicon oxide, these layers can be muchthicker and still have the same capacitance. The thicker layers avoidtunneling to the control gate that is an exponential function ofelectric fields but have an equivalent oxide thickness that is muchsmaller than their physical thickness.

Examples of this second category of nanolaminates include:oxide-nitride-ALD Al₂O₃, oxide-nitride-ALD HfO₂, and oxide-nitride-ALDZrO₂.

A third category of nanolaminates employs traps in the high-kdielectrics that have a larger energy depth with respect to theconduction band in the high-k trapping layer than those in the firstcategory. As a result, large offsets are not required between the layersin the nanolaminates and a wide variety of different nanolaminates arepossible using only high-k dielectrics in these nanolaminates. Theenergy depths of the traps can be adjusted by varying processconditions.

Examples of this third category of nanolaminates include: ALD HfO₂-ALDTa₂O₅-ALD HfO₂, ALD La₂O₃-ALD HfO₂-ALD La₂O₃, ALD HfO₂-ALD ZrO₂-ALDHfO₂, ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide-ALD ZrO₂-ALDLanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide, ALD Lanthanide Oxide-ALDHfO₂-ALD Lanthanide Oxide, and ALD Lanthanide Oxide-evaporated HfO₂-ALDLanthanide Oxide.

In one embodiment, the high-k gate dielectric layer is fabricated usingatomic layer deposition (ALD). As is well known in the art, ALD is basedon the sequential deposition of individual monolayers or fractions of amonolayer in a well controlled manner. Gaseous precursors are introducedone at a time to the substrate surface and between the pulses thereactor is purged with an inert gas or evacuated.

In the first reaction step, the precursor is saturatively chemisorbed atthe substrate surface and during subsequent purging the precursor isremoved from the reactor. In the second step, another precursor isintroduced on the substrate and the desired films growth reaction takesplace. After that reaction, byproducts and the precursor excess arepurged from the reactor. When the precursor chemistry is favorable, oneALD cycle can be performed in less than one second in a properlydesigned flow-type reactor.

ALD is well suited for deposition of high-k dielectrics such as AlO_(x),LaAlO₃, HfAlO₃, Pr₂O₃, Lanthanide-doped TiO_(x), HfSiON, Zr—Sn—Ti—Ofilms using TiCl₄ or TiI₄, ZrON, HfO₂/Hf, ZrAlXO_(y), CrTiO₃, andZrTiO₄.

The most commonly used oxygen source materials for ALD are water,hydrogen peroxide, and ozone. Alcohols, oxygen and nitrous oxide havealso been used. Of these, oxygen reacts very poorly at temperaturesbelow 600° C. but the other oxygen sources are highly reactive with mostof the metal compounds listed above.

Source materials for the above-listed metals include: zirconiumtetrachloride (ZrCl₄) for the Zr film, titanium tetraisopropoxide(Ti(OCH(CH₃)₂)₄) for the Ti film, trimethyl aluminum (Al(CH₃)₃) for theAl film, chromyl chromide (CrO₂Cl₂) for the Cr film, praseodymiumchloride (PrCl₃) for the Pr film, and hafnium chloride (HfCl₄) for theHf film. Alternate embodiments use other source materials.

Thin oxide films are deposited at a temperature that is high enough suchthat, when it is adsorbed to the substrate surface, the vaporized sourcematerial reacts with a molecular layer of a second source material orthat the vaporized source material becomes adsorbed and reacts with thesecond source material directed to the substrate surface in thesubsequent step. On the other hand, the temperature should be low enoughsuch that thermal breakdown of the source material does not occur orthat its significance in terms of the total growth rate of the film isvery small. Regarding the above-listed metals, the ALD process iscarried out at a temperature range of approximately 200-600° C.Alternate embodiments use other temperature ranges.

In another embodiment of the NROM memory transistor of the presentinvention, the high-k dielectric layers can be fabricated usingevaporation techniques. Various evaporation techniques are subsequentlydescribed for the high dielectric constant materials listed above.

Very thin films of TiO₂ can be fabricated with electron-gun evaporationfrom a high purity TiO₂ slug (e.g., 99.9999%) in a vacuum evaporator inthe presence of anion beam. In one embodiment, an electron gun iscentrally located toward the bottom of the chamber. A heat reflector anda heater surround the substrate holder. Under the substrate holder is anozonizer ring with many small holes directed to the wafer for uniformdistribution of ozone that is needed to compensate for the loss ofoxygen in the evaporated TiO₂ film. An ion gun with a fairly largediameter (3-4 in. in diameter) is located above the electron gun andargon gas is used to generate Ar ions to bombard the substrate surfaceuniformly during the film deposition to compact the growing TiO₂ film.

A two-step process is used in fabricating a high purity HfO₂ film. Thismethod avoids the damage to the silicon surface by Ar ion bombardment,such as that encountered during Hf metal deposition using dc sputtering.A thin Hf film is deposited by simple thermal evaporation. In oneembodiment, this is by electron-beam evaporation using a high purity Hfmetal slug (e.g., 99.9999%) at a low substrate temperature (e.g.,150°-200° C.). Since there is no plasma and ion bombardment of thesubstrate (as in the case of sputtering), the original atomically smoothsurface of the silicon substrate is maintained. The second step isoxidation to form the desired HfO₂.

The first step in the deposition of CoTi alloy film is by thermalevaporation. The second step is the low temperature oxidation of theCoTi film at 400° C. Electron beam deposition of the CoTi layerminimizes the effect of contamination during deposition. The CoTi filmsprepared from an electron gun possess the highest purity because of thehigh-purity starting material. The purity of zone—refined startingmetals can be as high as 99.999%. Higher purity can be obtained indeposited films because of further purification during evaporation.

A two step process in fabricating a high-purity ZrO₂ film avoids thedamage to the silicon surface by Ar ion bombardment. A thin Zr film isdeposited by simple thermal evaporation. In one embodiment, this isaccomplished by electron beam evaporation using an ultra-high purity Zrmetal slug (e.g., 99.9999%) at a low substrate temperature (e.g.,150°-200° C.). Since there is no plasma and ion bombardment of thesubstrate, the original atomically smooth surface of the siliconsubstrate is maintained. The second step is the oxidation to form thedesired ZrO₂.

The fabrication of Y₂O₃ and Gd₂O₃ films may be accomplished with a twostep process. In one embodiment, an electron gun provides evaporation ofhigh purity (e.g., 99.9999%) Y or Gd metal followed by low-temperatureoxidation technology by microwave excitation in a Kr/O₂ mixedhigh-density plasma at 400° C. The method of the present inventionavoids damage to the silicon surface by Ar ion bombardment such as thatencountered during Y or Gd metal deposition sputtering. A thin film of Yor Gd is deposited by thermal evaporation. In one embodiment, anelectron-beam evaporation technique is used with an ultra-high purity Yor Gd metal slug at a low substrate temperature (e.g., 150°-200° C.).Since there is no plasma or ion bombardment of the substrate, theoriginal atomically smooth surface of the silicon substrate ismaintained. The second step is the oxidation to form the desired Y₂O₃ orGd₂O₃.

The desired high purity of a PrO₂ film can be accomplished by depositinga thin film by simple thermal evaporation. In one embodiment, this isaccomplished by an electron-beam evaporation technique using anultra-high purity Pr metal slug at a low substrate temperature (e.g.,150°-200° C.). Since there is no plasma and ion bombardment of thesubstrate, the original atomically smooth surface of the siliconsubstrate is maintained. The second step includes the oxidation to formthe desired PrO₂.

The nitridation of the ZrO₂ samples comes after the low-temperatureoxygen radical generated in high-density Krypton plasma. The next stepis the nitridation of the samples at temperatures >700° C. in a rapidthermal annealing setup. Typical heating time of several minutes may benecessary, depending on the sample geometry.

The formation of a Y—Si—O film may be accomplished in one step byco-evaporation of the metal (Y) and silicon dioxide (SiO₂) withoutconsuming the substrate Si. Under a suitable substrate and two-sourcearrangement, yttrium is evaporated from one source, and SiO₂ is fromanother source. A small oxygen leak may help reduce the oxygendeficiency in the film. The evaporation pressure ratio rates can beadjusted easily to adjust the Y—Si—O ratio.

The prior art fabrication of lanthanum aluminate (LaAlO₃) films has beenachieved by evaporating single crystal pellets on Si substrates in avacuum using an electron-beam gun. The evaporation technique of thepresent invention uses a less expensive form of dry pellets of Al₂O₃ andLa₂O₃ using two electron guns with two rate monitors. Each of the tworate monitors is set to control the composition. The composition of thefilm, however, can be shifted toward the Al₂O₃ or La₂O₃ side dependingupon the choice of dielectric constant. After deposition, the wafer isannealed ex situ in an electric furnace at 700° C. for ten minutes in N₂ambience. In an alternate embodiment, the wafer is annealed at 800°-900°C. in RTA for ten to fifteen seconds in N₂ ambience.

FIG. 2 illustrates an energy-band diagram in accordance with the NROMflash transistor of FIG. 1. The diagram shows the relationship betweenE_(C), Φ, and the energy difference with respect to the conduction bandedge in the high-k trapping layer, E_(t).

FIG. 3 illustrates an energy-band diagram in accordance with a writeoperation in the transistor structure of FIG. 1 while FIG. 4 is theenergy-band diagram for an erase operation. The diagrams show theconduction band edge, E_(C), and the valence band edge, E_(V). BetweenE_(C) and E_(V) is the band gap where there are no states for electrons.The energy barrier, Φ, is the discontinuity in the conduction bands.

The high-k tunnel gate dielectric of the present invention reduces thebarriers between the substrate and gate insulator and/or between thefloating gate and the gate insulator. FIG. 5 illustrates a plot oftunneling current dependence on barrier height for various electricfields in accordance with the transistor structure of FIG. 1. This plotshows that the tunneling current at a fixed electric field can beincreased by orders of magnitude as a result of reducing the barriers.

In the specific case of Fowler-Nordheim tunneling, the expression thatdescribes the conduction in the insulator is J=AE² exp(−B/E) where J isthe current density in amps/cm², E is the electric field in theinsulator in volts/cm and A and B are constants for a particularinsulator. The constants depend on the effective mass and the electronbarrier energy of the insulator and are scaled with the barrier energy,Φ, as A ∝(1/Φ) and B ∝(Φ)3/2.

For the case of the commonly used gate insulator, SiO₂, the equationabove renders A(SiO₂—Si)=5.5×10⁻¹⁶ amps/volt² and B(SiO₂—Si)=7.07×10⁷V/cm. If a new barrier of Φ=1.08 eV is utilized, likely values for A andB can be extrapolated from the above equations. In this case, A(Φ=1.08eV)=1.76×10⁻¹⁵ amps/volt² and B(Φ=1.08 eV)=1.24×10⁷ V/cm.

Curves of J versus the barrier energy, F, are shown in FIG. 5 forseveral values of E. For a given tunneling current, lower barriersrequire lower electric fields. As an example, an SiO₂ barrier of 3.2 eVhas an electric field of 6×10⁶ V/cm while for the same tunnelingcurrent, a high-k dielectric with a 1.08 eV barrier requires only anelectric field of 7×10⁵ V/cm. If the thicknesses of the two dielectricsare the same then the voltage required will be about 8.6 times less forthe same current. If the high-k dielectric has a dielectric constant of28, then the equivalent oxide thickness (EOT) will be 7 times less thanthe actual thickness of the high-k dielectric.

The NROM memory transistors of the present invention can thus bedesigned with very small equivalent oxide thicknesses and scaled intothe 50 nm dimensions without drain turn-on problems, short-channeleffects, and punch through. Additionally, retention times will decreasedue to more thermal excitation and emission of electrons over thesmaller barriers.

FIG. 6 illustrates a functional block diagram of a memory device 600that can incorporate the flash memory cells of the present invention.The memory device 600 is coupled to a processor 610. The processor 610may be a microprocessor or some other type of controlling circuitry. Thememory device 600 and the processor 610 form part of an electronicsystem 620. The memory device 600 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentinvention.

The memory device includes an array of flash memory cells 630 that canbe NROM flash memory cells. The memory array 630 is arranged in banks ofrows and columns. The control gates of each row of memory cells iscoupled with a wordline while the drain and source connections of thememory cells are coupled to bitlines. As is well known in the art, theconnection of the cells to the bitlines depends on whether the array isa NAND architecture or a NOR architecture.

An address buffer circuit 640 is provided to latch address signalsprovided on address input connections A0-Ax 642. Address signals arereceived and decoded by a row decoder 644 and a column decoder 646 toaccess the memory array 630. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends on the density and architecture of thememory array 630. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 600 reads data in the memory array 630 by sensingvoltage or current changes in the memory array columns usingsense/buffer circuitry 650. The sense/buffer circuitry, in oneembodiment, is coupled to read and latch a row of data from the memoryarray 630. Data input and output buffer circuitry 660 is included forbi-directional data communication over a plurality of data connections662 with the controller 610. Write circuitry 655 is provided to writedata to the memory array.

Control circuitry 670 decodes signals provided on control connections672 from the processor 610. These signals are used to control theoperations on the memory array 630, including data read, data write, anderase operations. The control circuitry 670 may be a state machine, asequencer, or some other type of controller.

Since the NROM memory cells of the present invention use a CMOScompatible process, the memory device 600 of FIG. 6 may be an embeddeddevice with a CMOS processor.

The flash memory device illustrated in FIG. 6 has been simplified tofacilitate a basic understanding of the features of the memory. A moredetailed understanding of internal circuitry and functions of flashmemories are known to those skilled in the art.

CONCLUSION

In summary, an NROM cell can use a high-k dielectric as the trappinglayer. The high-k dielectric can be fabricated using atomic layerdeposition, evaporation, or a combination of the two processes. Thehigh-k dielectric enables smaller write and erase voltages to be usedand eliminates drain turn-on problems, short-channel effects, and punchthrough.

The NROM flash memory cells of the present invention may be NAND-typecells, NOR-type cells, or any other type of array architecture.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A method for fabricating an NROM memory cell, the method comprising:creating a plurality of source/drain regions by doping portions of asubstrate; forming a nanolaminate gate dielectric layer on the substratesubstantially between the plurality of source/drain regions, whereinforming the gate dielectric layer comprises forming one of the followingstructures: oxide-HfO₂-oxide, oxide-HfO₂-oxide, oxide-ZrO₂-oxide,oxide-ZrO₂-oxide, oxide-ZrSnTiO-oxide, oxide-ZrON-oxide,oxide-ZRON-oxide, oxide-ZrAlO-oxide, oxide-ZrTiO₄-oxide,oxide-Al₂O₃-oxide, oxide-La₂O₃-oxide, oxide-LaAlO₃-oxide,oxide-LaAlO₃-oxide, oxide-HfAlO₃-oxide, oxide-HfSiON-oxide,oxide-Y₂O₃-oxide, oxide-Gd₂O-oxide, oxide-Ta₂O₅-oxide, oxide-TiO₂-oxide,oxide-TiO₂-oxide, oxide-Pr₂O₃-oxide, oxide-Pr₂O₃-oxide,oxide-CrTiO₃-oxide, or oxide-YSiO-oxide; and forming a gate on the gatedielectric layer.
 2. The method of claim 1 wherein the plurality ofsource/drain regions are p+regions in an n+ substrate.
 3. The method ofclaim 1 wherein the plurality of source/drain regions are n+regions in ap+ substrate.
 4. The method of claim 1 wherein the substrate is silicon.5. The method of claim 1 wherein gate is polysilicon.
 6. The method ofclaim 1 wherein the gate dielectric layer is formed from atomic layerdeposition.
 7. A method for fabricating an NROM memory cell, the methodcomprising: creating a plurality of source/drain regions by dopingportions of a substrate; forming a nanolaminate gate dielectric layer onthe substrate substantially between the plurality of source/drainregions, wherein forming the gate dielectric layer comprises forming oneof the following structures: oxide-nitride-Al₂O₃, oxide-nitride-HfO₂, oroxide-nitride-ZrO₂; and forming a gate over the dielectric layer.
 8. Amethod for fabricating an NROM memory cell, the method comprising:creating a plurality of source/drain regions by doping portions of asubstrate; forming a nanolaminate gate dielectric layer on the substratesubstantially between the plurality of source/drain regions, whereinforming the gate dielectric layer comprises forming one of the followingstructures: HfO₂—Ta₂O₅—HfO₂, La₂O₃—HfO₂—La₂O₃, HfO₂—ZrO₂—HfO₂,Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide-ZrO₂-Lanthanide Oxide,Lanthanide Oxide-HfO₂—Lanthanide Oxide, or LanthanideOxide-HfO₂-Lanthanide Oxide; and forming a gate over the dielectriclayer.
 9. The method of claim 1 wherein forming the gate dielectriclayer comprises an atomic layer deposition technique.
 10. The method ofclaim 1 wherein forming the gate dielectric layer comprises anevaporation technique.
 11. The method of claim 1 wherein forming thegate dielectric layer comprises an atomic layer deposition technique andan evaporation technique.
 12. A method for fabricating an NROM memorycell, the method comprising: creating a plurality of source/drainregions by doping portions of a substrate; forming a tunnel oxide layeron the substrate substantially between the plurality of source/drainregions; forming a gate dielectric layer with an evaporation techniqueon the tunnel oxide layer, the gate dielectric layer comprising one ofthe following: HfO₂, ZrO₂, ZrON, LaAlO₃, Y₂O₃, Gd₂O, TiO₂, CrTiO₃, orYSiO; forming a gate oxide layer on the gate dielectric layer; andforming a gate on the gate oxide layer.
 13. The method of claim 12wherein forming the tunnel oxide and gate oxide layers includesdeposition of the layers.
 14. A method for fabricating an NROM memorycell, the method comprising: creating a plurality of source/drainregions by doping portions of a substrate; forming a tunnel oxide layeron the substrate substantially between the plurality of source/drainregions; forming a gate dielectric layer with an atomic layer depositiontechnique on the tunnel oxide layer, the gate dielectric layer comprisesone of: HfO₂, ZrO₂, ZrSnTiO, ZrON, ZrAlO, ZrTiO₄, Al₂O₃, La₂O₃, LaAlO₃,HfAlO₃, HfSiON, Ta₂O₅, TiO₂, or Pr₂O₃; forming a gate oxide layer on thegate dielectric layer; and forming a gate on the gate oxide layer. 15.The method of claim 14 wherein the tunnel oxide, gate dielectric, andoxide layers are formed by deposition.
 16. A method for fabricating anNROM memory cell, the method comprising: creating a plurality ofsource/drain regions by doping portions of a substrate; depositing atunnel oxide layer on the substrate substantially between the pluralityof source/drain regions; depositing a nitride layer on the gatedielectric layer; and depositing a gate dielectric layer with an atomiclayer deposition technique on the nitride layer, the gate dielectriclayer comprising one of dielectric materials: Al₂O₃, HfO₂, or ZrO₂;forming a control gate on the oxide insulator material.
 17. The methodof claim 16 wherein the dielectric materials have a lower conductionband edge than silicon nitride.
 18. A method for fabricating an NROMmemory cell, the method comprising: creating a plurality of source/drainregions by doping portions of a substrate; forming a nanolaminate gatedielectric layer with an atomic layer deposition technique on thesubstrate substantially between the plurality of source/drain regions,the gate dielectric layer comprising one of: HfO₂—Ta₂O₅—HfO₂,La₂O₃—HfO₂—La₂O₃, HfO₂—ZrO₂—HfO₂, Lanthanide (Pr, Ne, Sm, Gd, and Dy)Oxide-ZrO₂-Lanthanide Oxide, Lanthanide Oxide-HfO₂-Lanthanide Oxide, orLanthanide Oxide-HfO₂-Lanthanide Oxide; and forming a gate on the gatedielectric material.
 19. The method of claim 18 wherein eachsource/drain region is an n+ region that can act as either a source or adrain in response to a direction of operation of the cell.